NXP Semiconductors /MIMXRT1064 /IOMUXC /SW_MUX_CTL_PAD_GPIO_B1_12

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Interpret as SW_MUX_CTL_PAD_GPIO_B1_12

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MUX_MODE 0 (DISABLED)SION

SION=DISABLED

Description

SW_MUX_CTL_PAD_GPIO_B1_12 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

1 (ALT1): Select mux mode: ALT1 mux port: LPUART5_TX of instance: lpuart5

2 (ALT2): Select mux mode: ALT2 mux port: CSI_PIXCLK of instance: csi

3 (ALT3): Select mux mode: ALT3 mux port: ENET_1588_EVENT0_IN of instance: enet

4 (ALT4): Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO28 of instance: flexio2

5 (ALT5): Select mux mode: ALT5 mux port: GPIO2_IO28 of instance: gpio2

6 (ALT6): Select mux mode: ALT6 mux port: USDHC1_CD_B of instance: usdhc1

9 (ALT9): Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO28 of instance: flexio3

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_B1_12

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